LIBRARY IEEE;
   USE IEEE.STD_LOGIC_1164.ALL;
   USE IEEE.STD_LOGIC_ARITH.ALL;
   USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  
   ENTITY demux IS
   PORT(   din:          in std_logic_vector(17 downto 0);
           clkin:        in std_logic;
           cn:           in std_logic_vector(7 downto 0);
           daa,dbb,dcc,ddd:  out std_logic_vector(7 downto 0);
           dee,dff,dgg,dhh:  out std_logic_vector(7 downto 0);
           clk_12m,sel:  out std_logic;
           led:       out std_logic_vector(15 downto 0) );                 
         END demux;       
   ARCHITECTURE BE OF demux IS
      
        signal da,db,dc,dd:       std_logic_vector(7 downto 0);
        signal de,df,dg,dh:       std_logic_vector(7 downto 0);
      --  signal din:       std_logic_vector(9 downto 0);
    BEGIN
      process(clkin)
        begin         
          if clkin'event and clkin='1'  then
             if conv_integer(cn(1 downto 0))=0 then
                da<=din(7 downto 0);
                de<=din(15 downto 8);
             elsif conv_integer(cn(1 downto 0))=1 then
                db<=din(7 downto 0);
                df<=din(15 downto 8);
             elsif conv_integer(cn(1 downto 0))=2 then
                dc<=din(7 downto 0);
                dg<=din(15 downto 8);
             elsif conv_integer(cn(1 downto 0))=3 then
                ddd<=din(7 downto 0);
                dhh<=din(15 downto 8);
                daa<=da;
                dbb<=db;
                dcc<=dc;
                dee<=de;
                dff<=df;
                dgg<=dg;
             end if;
             if conv_integer(cn(2 downto 0))=2 then
                led(0)<=not da(7);
                led(2)<=not db(7);
                led(4)<=not dc(7);
                led(6)<=not dd(7);
                led(8)<=not de(7);
                led(10)<=not df(7);
                led(12)<=not dg(7);
                led(14)<=not dh(7);
             elsif conv_integer(cn(2 downto 0))=6 then
                led(1)<=not da(7);
                led(3)<=not db(7);
                led(5)<=not dc(7);
                led(7)<=not dd(7);
                led(9)<=not de(7);
                led(11)<=not df(7);
                led(13)<=not dg(7);
                led(15)<=not dh(7);
             end if;
             clk_12m<=not cn(2);
             sel<=cn(2);
          end if;         
        end process;           
    --    clk_12m<=not cn(2);
    --    sel<=cn(2);     
   end be;